1. Field of the Art
The present invention generally relates to oscillator circuits, and more particularly to an oscillator circuit for providing a CPU clock oscillator signal.
2. Discussion of the Related Art
In recent years, the advancement of integrated circuit technology has precipitated the proliferation of a wide variety of hand held and portable computing devices. For example, laptop and notebook computers are known which possess tremendous processing speed and capability, and can quite easily fit in a briefcase for convenient transport to remote work sites. Indeed, business people frequently tote computers along for work at home or during travel. Even smaller devices, such as pocket-sized electronic organizers and calculators are designed with tremendous processing capabilities and are sized to readily fit in a suit breast pocket, for example. Calculators, designed for scientific as well as business disciplines are capable of processing exceeding sophisticated mathematical equations, and are widely used by both students and professionals. Pocket-sized electronic organizers have become increasingly popular as a surrogate to daily planners and are generally designed to maintain scheduling information, to-do lists, telephone directories, etc.
While the above-listed portable electronic devices may differ vastly in their relative designs and functional capabilities, a salient design feature shared among them all is portability and, therefore, the ability to operate from battery power. In this regard, the battery is a limited resource which defines the usable or work life of the device. Under normal use, battery packs for portable computers generally last for several hours, while the batteries in hand-held calculators and electronic organizers generally last for several months.
It can be appreciated that an important feature of portable electronic devices is their ability to operate from very low power and, therefore, conserve battery life. A variety of approaches and design configurations are presently known that seek to achieve this goal. For example, laptop computers having a permanent disk drive will typically power-down the drive when it is not in use, due to the relatively large power requirements of the drive motor. While this degrades the performance of the computer when the permanent drive needs to be accessed (due to the time required to bring the drive up to speed), it substantially lengthens the work life of the battery pack, since disk access is usually infrequent. Another technique that is used to preserve battery life in portable computers, pocket organizers, and other small electronic devices that utilize a CPU, is to invoke what is commonly referred to as a "sleep" state, when the CPU becomes inactive.
More specifically, and as understood by persons skilled in the art, a CPU (e.g., microprocessor, microcontroller, etc.) is often inactive, insofar as no useful computations are presently being carried out for the user. For example, in an application where a portable computing device is waiting for a user to enter a keystroke, the CPU may be executing delay instructions in an infinite loop or, alternatively, the CPU may be waiting for an interrupt. In situations like this, it is desirable to place the CPU in a "sleep" state, whereby sufficient power is provided to the CPU to maintain the integrity of the data stored in its internal registers, but the power is otherwise conserved by halting other activity. Thus, a CPU is often designed to operate in a "normally active" state as well as a "sleep" state of operation. Frequently, and for reasons described below, the sleep state of operation is further subdivided into two separate states of operation. A first, or "low power" state, is provided in which the CPU is substantially shut down, except for the CPU oscillator circuit portion. In the second, or "off" state, the entire CPU, including the oscillator circuit portion, is shut down.
It is known to use a device known as a phase locked loop to provide internal CPU clock signals. In such devices, an external oscillator signal is input to the phase locked loop, which can be configured to provide a coherent (i.e., in-phase or synchronous) output signal having a much higher frequency. As is known, a voltage controlled oscillator lies at the heart of a phase locked loop, and provides an oscillatory output signal that increases in frequency as the magnitude of the voltage input increases. By feeding the oscillatory signal output from the voltage controlled oscillator and the external oscillatory signal into a multiplier--the output of which is input to the voltage controlled oscillator--it is known that the output of the voltage controlled oscillator will "synch-up" with the oscillatory input signal. However, there is usually some delay period associated with this initial synchronization. When output of the voltage controlled oscillator is passed through a frequency divider before being routed to the multiplier, the output of the frequency divider, instead of the phase locked loop, will synch-up with the oscillatory input signal. As a result, the output of the phase locked loop will be an oscillating signal of much higher frequency than the signal input. Accordingly, the parameters of the divider circuitry dictate the frequency increase achieved by the phase locked loop oscillator circuitry.
While the phase locked loop circuitry described above realizes certain performance advantages, (i.e., precise synchronization of the CPU clock with the external bus clock), there are shortcomings associated with this approach. For example, it is known that phase locked loop devices are analog devices, and typically consume more power than counterpart digital devices. In an environment where power conservation is critical, it is appreciated that the use of analog circuitry unduly consumes battery resources. It is, therefore, desired to shut down the phase locked loop clock oscillator, (i.e., from the "low power" mode to the "off" mode). However, when transferring from the "off" mode to the normally-active mode, an excessive amount of time is required in order to bring the CPU clock speed up to its stable state. That is, an excessive amount of time is required to synch-up the output of the phase locked loop.
As previously mentioned, CPU oscillator circuits generally provide two separate "sleep" states of operation. In the first, or "low power" state, the CPU oscillator circuit portion is operating normally, while the remainder of the CPU is shut down. A second, or "off" sleep state, is provided in which the entire CPU, including the oscillator circuit portion, is shut down. On the one hand and in order to achieve maximum power conservation, it is desired to enter the "off" state whenever possible. On the other hand, however, when excessively entering and leaving the "off" state, significant performance diminution is noted, due to the time required for the phase locked loop to synch-up. Importantly, the time expended during the "synch-up" period accounts for significant power consumption, particularly when the oscillator circuit is repeatedly turned on and off. Accordingly, the CPU must be designed with sufficient "intelligence" to determine when to enter the low power state and when to enter the off state.
This "intelligence" may be rather simply provided by way of a time-out. That is, the CPU may be normally configured to enter a low power sleep state and, upon entering that state, begin a timer. After a time-out of a predetermined period of time, if the CPU has not been awakened from the sleep state to operate in the normally active state, then the CPU will be transferred to the off state. Alternatively, more sophisticated "intelligence" may be designed into the CPU, whereby the CPU analyzes the sequence of instructions executed just prior to entering a sleep state. It may be learned that certain instructions executed just prior to entering in a sleep state are typically associated with a very long inactive period, whereby the oscillator circuitry should be shut down. In instances such as these, it would be desirable to have the CPU anticipate the long sleep state and directly enter the off state, without awaiting a time-out. It can be understood, however, that this approach would unduly increase the complexity of the CPU.
It can therefore be appreciated that there is need to provide an oscillator circuit for generating an internal CPU clock that operates at low power when active and, at the same time, may be transferred between sleep and active states in a relatively short period of time.